Glitch Free Switch Timing Constraints
A glitch-free clock multiplexer switches between CLK0 and CLK1 based on SEL without truncating clock pulses. When SEL changes, OUT_CLK continues following the currently active clock until that clock's next HIGH-to-LOW transition, at which point OUT_CLK halts at 0. It remains 0 until the newly selected clock undergoes a HIGH-to-LOW transition, after which OUT_CLK follows the new clock.
Four signals are shown: CLK0 (active clock, period 2), CLK1 (secondary clock input, period 4), SEL (select input) and OUT_CLK (output, initially 0).
Trace OUT_CLK across all 16 time steps.
Constraints
OUT_CLKmust remain 0 during the dead time between the two clock domains.- A clock transition is triggered only on a HIGH-to-LOW edge.
Topics
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