Glitch Free Switch Unrelated Clocks
Changing operating frequencies on the fly requires switching between independent oscillators without generating runt pulses or glitches. The glitch-free clock multiplexer is the industry standard mechanism for safely transitioning between asynchronous clock domains in modern system-on-chips.
The circuit must route either clk0 or clk1 to clk_out based on the state of the sel signal.
| sel | clk_out (steady state) | |-------|--------------------------| | 0 | clk0 | | 1 | clk1 |
When sel transitions, the currently active clock must be cleanly disabled before the new clock is enabled. The enable signal for each clock domain must only change when its respective clock is low. This ensures the output clock is never truncated during a high phase. The two clock domains must be cross-coupled so that a new clock is never enabled until the previous clock has been fully disabled.
Constraints
- Use negative-edge triggered flip-flops to sample the select and feedback signals.
- Implement cross-coupled feedback to ensure mutual exclusion of the clock enable signals.
- Do not use any positive-edge triggered sequential logic.
Topics
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