Synchronous Clock Switch
Dynamic voltage and frequency scaling architectures shift between clock frequencies to optimize power. When switching between integer-divided clocks that share the same phase and source, a simplified synchronous switch avoids the latency of a full asynchronous glitch-free multiplexer.
Route clk_fast to clk_out when sel is 0. Route clk_slow to clk_out when sel is 1. To prevent runt pulses during the transition, the sel signal must be aligned to the faster clock domain before controlling the multiplexer.
Constraints
- Use exactly one D flip-flop.
- Clock the flip-flop using the
clk_fastdomain. - Use a single 2-to-1 multiplexer for the clock selection.
- Do not use any additional sequential logic elements.
Topics
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