Naive Clock Multiplexer Glitch Analysis
A pure combinational 2-to-1 multiplexer dynamically switches the clock source for a downstream circuit based on an asynchronous select signal.
Four signals are shown: CLK_A (fast clock, period 2), CLK_B (slow clock, period 4), SEL (asynchronous select input), and OUT_CLK (multiplexed clock output). The multiplexer routes CLK_A to OUT_CLK when SEL is 0, and routes CLK_B to OUT_CLK when SEL is 1.
Trace the OUT_CLK signal across all 12 time steps to observe how an asynchronous switch introduces chopped clock pulses.
Constraints
- The multiplexer evaluates instantaneously without delay.
- The output strictly follows the selected input at the current time step.
- Pay close attention to time steps where
SELtransitions while the active and inactive clocks are at different logic levels.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.