Wake Up Logic for Gated Clock
Mobile processors and IoT sensors power down their clock trees to save energy. When the clock is off, standard synchronous logic is frozen and cannot detect the signal to turn the clock back on.
Design an asynchronous wake-up controller that manages a clock gate. The circuit receives a continuous clk_in, a synchronous active-high sleep_req, and an asynchronous active-high wake_irq.
The system maintains an internal enable state. When sleep_req is high during a rising clock edge, the enable state drops to 0. When wake_irq goes high, the enable state is asynchronously forced to 1 immediately, regardless of the clock. The final output clk_out is the logical AND of clk_in and the system enable.
| sleep_req | wake_irq | Clock Edge | Next Enable State | |-------------|------------|------------|-------------------| | X | 1 | Asynchronous | 1 (Awake) | | 0 | 0 | Rising | 1 (Awake) | | 1 | 0 | Rising | 0 (Sleep) |
Constraints
- Use a D flip-flop with an asynchronous preset/set pin to hold the system enable state.
- Do not use a latch for the clock gate: use a simple AND gate for this idealized implementation.
- The asynchronous set must override the synchronous D input.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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