Local versus Distributed Gating Timing

Placing a clock gate deep in a logic path introduces insertion delay that skews the local clock relative to the global clock. A local clock gating cell computes the logical AND of CLK and EN, but its output GCLK is delayed by exactly one time step. A positive-edge-triggered D flip-flop captures the value of D at every LOW-to-HIGH transition of GCLK and holds it until the next rising edge.

Five signals are shown: CLK (source clock, period 2), EN (enable input), D (data input), GCLK (gated clock output, initially 0), and Q (flip-flop output, initially 0).

Trace GCLK and Q across all 12 time steps.

Constraints

• GCLK at any given time step is the logical AND of CLK and EN from the previous time step.
• Q updates its value to match D exactly at the time step where GCLK transitions from 0 to 1.
• EN transitions only when CLK is LOW to prevent clock glitches.

Topics

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