Unconnected Input Port Floating to High Z
A system timer relies on a 4-bit synchronous counter to track active processing cycles.
Expected behavior:
| RST | EN | CLK | Q (next) | |-------|------|-------|------------| | 1 | X | ↑ | 0 | | 0 | 1 | ↑ | Q + 1 | | 0 | 0 | ↑ | Q |
The top-level circuit instantiates a counter component to handle this logic. Simulation shows that after a successful reset, the counter output Q remains at 0 indefinitely, even when the top-level EN input is driven to 1. The counter is sitting idle. Inspect the circuit and correct the fault.
Constraints
- Do not modify the internal logic of the instantiated counter component.
- You may only add or modify wires in the top-level schematic.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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