Up/Down Counter: Direction Change Mid-Count Waveform
A 3-bit synchronous up/down counter updates its internal state on every positive clock edge, incrementing by 1 when UP_DN is HIGH and decrementing by 1 when UP_DN is LOW. Five signals are shown: CLK (clock, period 2), UP_DN (direction input), and Q2, Q1, Q0 (counter outputs). The initial state of the counter is 5 (Q2=1, Q1=0, Q0=1). Trace Q2, Q1, and Q0 across all 12 time steps.
Constraints
- Output changes only occur on the LOW-to-HIGH transitions of
CLK. - The direction input
UP_DNis evaluated exactly at the rising edge of the clock. - Changes to
UP_DNmid-cycle do not affect the output until the next rising clock edge.
Topics
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