Verilog
Blocking vs nonblocking assignments in Verilog
When to use = and when to use <= in Verilog: what each assignment does, why mixing them breaks a shift register, and the rules that prevent simulation races.
Blog
Digital design, explained with working code
Guides to Verilog, SystemVerilog, VHDL and logic design, with code to copy and problems to solve on Codiode.