2-FF Synchronizer: Metastability Resolution
A two-flip-flop synchronizer uses two positive-edge-triggered D flip-flops to mitigate metastability by providing a full clock cycle for the first stage to resolve before the second stage samples the signal.
Four signals are shown: CLK (clock, period 10), ASYNC_IN (asynchronous input), Q1 (first stage output, initially 0), and Q2 (second stage output, initially 0). The asynchronous input transitions exactly on the first clock rising edge, causing Q1 to violate setup/hold requirements and become metastable. Assume the metastable state persists for exactly 8 time steps before resolving to a stable HIGH state.
Trace Q1 and Q2 across all 24 time steps.
Constraints
- Use "X" to denote any metastable or indeterminate time step.
- Both flip-flops are positive-edge-triggered and capture the value of their input immediately prior to the clock edge.
- The clock period is 10 time steps, meaning it alternates state every 5 time steps.
Topics
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