Gray-Code Counter for Safe Multi-Bit CDC
Clock domain crossing of multi-bit signals routinely causes catastrophic data corruption if standard binary encoding is used.
A 4-bit asynchronous FIFO pointer must be passed from the write clock domain clk_w to the read clock domain clk_r. The design uses a standard 2-flip-flop synchronizer on each individual bit of the pointer. Two encodings are evaluated for the pointer: a standard binary counter B[3:0] and a Gray-code counter G[3:0].
Analyze the behavior of both counters during state transitions across the asynchronous boundary. Determine the vulnerability of each encoding to multi-bit metastability and identify the safe synchronization strategy.
Constraints
- Standard 2-FF synchronizers are applied to each individual bit of the bus.
- The read clock
clk_ris completely asynchronous to the write clockclk_w. - No handshake protocol or FIFO empty/full logic is evaluated: focus strictly on the pointer bus transit.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.