Pulse Synchronizer
Passing control signals between asynchronous clock domains requires specialized synchronization logic to prevent data loss. When a control pulse in the source domain is shorter than the period of the destination clock, a standard two-stage synchronizer will miss the event entirely.
The circuit must capture a narrow pulse_in on the source clock clk_tx and safely transfer it to the destination clock clk_rx. The source domain must convert the pulse into a level change. The destination domain must synchronize this level and generate a single-cycle pulse_out for every level transition.
| Clock Event | pulse_in | Internal Toggle State | pulse_out | |-------------|------------|-----------------------|-------------| | clk_tx ↑ | 1 | Toggles | 0 | | clk_rx ↑ | 0 | Holds | 0 | | clk_rx ↑ | 0 | Holds | 1 | | clk_rx ↑ | 0 | Holds | 0 |
Constraints
- Implement a toggle flip-flop in the
clk_txdomain to stretch the incoming pulse. - Implement a two-stage flip-flop synchronizer in the
clk_rxdomain. - Implement an edge detector in the
clk_rxdomain to recover the pulse. - Tie all flip-flop reset pins to the asynchronous active-high
rstsignal. - Use only D flip-flops and basic combinational logic gates.
Topics
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