Analyze: Simulation Delta Cycles
Hardware simulators use an event-driven execution model where zero-delay events are separated into microscopic time steps called delta cycles.
The code below models a cross-coupled register pair with combinational feedback.
wire d1 = ~q2;
wire d2 = ~q1;
always @(posedge clk) q1 <= d1;
always @(posedge clk) q2 <= d2;At time T=0, q1 is 0 and q2 is 1. The first rising edge of clk occurs at T=10.
Trace the simulation event queue at T=10. Determine the exact sequence of evaluation, scheduling, and updates across the Active and Nonblocking Assignment (NBA) regions.
Constraints
- Assume a standard IEEE 1364 Verilog event queue.
- The
clktransition is the only external event at T=10. - Continuous assignments execute in the Active region.
- Delta cycles are zero-delay steps that occur within the same simulation time step.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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