Debug: Read Before Write In Sequential Block
A synchronous logic block evaluates the AND of inputs A and B, XORs the result with input C, and registers the final output Y on the rising clock edge. This pattern is common in pipelined control paths where intermediate combinatorial values must be consumed in the same cycle.
Expected behavior:
| Cycle | A | B | C | Y | |-------|-----|-----|-----|-----| | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 1 | 0 | 1 | | 2 | 0 | 1 | 1 | 1 | | 3 | 1 | 1 | 1 | 0 |
The design synthesizes without errors but behaves exactly one clock cycle behind the intended specification. Simulation shows Y = 0 during cycle 1. The output only updates to the expected 1 in cycle 2. Inspect the circuit and correct the fault.
Constraints
- Do not remove the final output register.
- Only modify the faulty connection or component causing the extra cycle delay.
- The circuit must complete the logic evaluation and register the result in a single clock cycle.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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