Debug: Polarity Mismatch in Reset Condition
A D flip-flop with an active-high asynchronous reset stores a single bit of state and clears its output to zero when the reset signal is asserted.
Expected behavior:
| rst | clk | D | Q | |-------|-------|-----|--------| | 1 | X | X | 0 | | 0 | 0 | X | Q_prev | | 0 | ↑ | 0 | 0 | | 0 | ↑ | 1 | 1 |
Simulation shows Q = 0 continuously when rst = 0 and clk transitions from 0 to 1 with D = 1. The circuit fails to capture valid data because it behaves as if the reset is permanently active during normal operation. Inspect the circuit and correct the fault.
Constraints
- Do not modify the clock or data input routing.
- The corrected circuit must use exactly one D flip-flop component.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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