Analyze: Array Initialization vs Hardware Reset
Initializing large memory structures requires careful consideration of physical hardware constraints rather than software-like convenience.
The provided RTL block contains a 1024-entry, 32-bit wide memory array named mem_array. An asynchronous active-low reset signal rst_n triggers a for loop that iterates from 0 to 1023, assigning 0 to every index of mem_array in a single clock cycle.
Evaluate the synthesis implications of this logic. Determine why this block behaves perfectly in simulation but causes massive routing congestion and timing failures during synthesis.
Constraints
- Assume a standard ASIC standard cell library where registers are implemented as discrete D flip-flops.
- The memory array is not mapped to an SRAM macro.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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