Debug: Clock Enable in Sensitivity List
A clock-enabled register stores data only when the enable signal is active, preventing unnecessary switching power in digital designs.
Expected behavior:
| clk | rst | en | d | q (next) | |-------|-------|------|-----|------------| | X | 1 | X | X | 0 | | ↑ | 0 | 1 | 0 | 0 | | ↑ | 0 | 1 | 1 | 1 | | ↑ | 0 | 0 | X | q (prev) | | 0/1 | 0 | X | X | q (prev) |
Simulation shows q = 0 when clk = 0, rst = 0, en = 1, and d = 0 immediately following a state where q = 1. The output updates on the rising edge of the enable signal instead of waiting for the clock. Inspect the design and correct the fault.
Constraints
- The design must use a single clock domain driven by
clk. - Do not instantiate structural latches.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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