4-Bit Counter from Timing Diagram: Reverse Engineer
Hardware specifications often arrive as timing diagrams from systems engineers rather than clean truth tables. Reverse-engineering a state machine from an observed waveform is a standard workflow for integrating undocumented IP blocks.
Construct a synchronous counter that generates the exact 4-bit sequence observed in the logic analyzer trace below. The sequence loops indefinitely.
| Cycle | Q3 | Q2 | Q1 | Q0 | |-------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | | 1 | 1 | 0 | 0 | 0 | | 2 | 1 | 1 | 0 | 0 | | 3 | 1 | 1 | 1 | 0 | | 4 | 1 | 1 | 1 | 1 | | 5 | 0 | 1 | 1 | 1 | | 6 | 0 | 0 | 1 | 1 | | 7 | 0 | 0 | 0 | 1 | | 8 | 0 | 0 | 0 | 0 |
Constraints
- Use exactly four D flip-flops.
- Clock all flip-flops synchronously using the
clksignal. - Implement an active-high synchronous reset using the
rstsignal to force the state back to0000. - Derive the next-state logic using only combinational gates.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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