4-Bit Step-3 Counter: Custom Sequence
Phase generators and memory address sequencers often require non-standard counting intervals to align with specific timing windows. The step-3 counter generates a custom sequence that increments by three on every clock cycle.
The circuit must produce a 4-bit output using four 1-bit signals: Q3 (MSB), Q2, Q1, and Q0 (LSB). The counter must follow the valid sequence 0, 3, 6, 9, 12, and loop back to 0. It must be self-correcting: if the circuit enters any of the 11 invalid states, the next clock edge must transition the state to 0. An active-high 1-bit rst signal synchronously forces the output to 0.
| Q3 | Q2 | Q1 | Q0 | Next State (Q3 Q2 Q1 Q0) | |------|------|------|------|----------------------------------| | 0 | 0 | 0 | 0 | 0011 | | 0 | 0 | 1 | 1 | 0110 | | 0 | 1 | 1 | 0 | 1001 | | 1 | 0 | 0 | 1 | 1100 | | 1 | 1 | 0 | 0 | 0000 |
For all other 11 state combinations of Q3, Q2, Q1, and Q0, the next state must be 0000.
Constraints
- Use D flip-flops for all sequential elements.
- Implement synchronous active-high reset logic.
- Map all 11 invalid states explicitly to 0 in the next-state logic.
Topics
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