3-Bit Gray Code Counter
Asynchronous FIFOs and clock domain crossing circuits rely on pointers that change only one bit at a time to prevent metastability. The 3-bit Gray code counter generates this safe sequence, cycling through all eight possible states without intermediate glitches.
The counter updates its 3-bit output {Q2, Q1, Q0} on the rising edge of clk. When rst is 1, the output synchronously resets to 000. When rst is 0, the counter follows the standard 3-bit Gray code sequence.
| Q2 | Q1 | Q0 | D2 | D1 | D0 | |------|------|------|------|------|------| | 0 | 0 | 0 | 0 | 0 | 1 | | 0 | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 0 | 1 | 0 | | 0 | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 | 1 | 1 | | 1 | 1 | 1 | 1 | 0 | 1 | | 1 | 0 | 1 | 1 | 0 | 0 | | 1 | 0 | 0 | 0 | 0 | 0 |
Constraints
- Use exactly three D flip-flops for state storage.
- Implement the next-state logic using basic combinational logic gates.
- The reset must be synchronous and active-high.
- Do not use high-level arithmetic components like adders.
Topics
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