Counter: Distinguishing Logic Error from Stuck-at Fault
A 3-bit synchronous up-counter tracks events by incrementing its binary value on every clock cycle.
Expected behavior:
| Current State (Q2, Q1, Q0) | Next State (Q2, Q1, Q0) | |----------------------------------|-------------------------------| | 0 0 0 | 0 0 1 | | 0 0 1 | 0 1 0 | | 0 1 0 | 0 1 1 | | 0 1 1 | 1 0 0 | | 1 0 0 | 1 0 1 | | 1 0 1 | 1 1 0 | | 1 1 0 | 1 1 1 | | 1 1 1 | 0 0 0 |
Simulation shows an incorrect count sequence of 0, 1, 6, 7, 4, 5, 2, 3. Diagnostics rule out a stuck-at fault because Q2 successfully toggles between 0 and 1. The failure is a logic error causing Q2 to transition at incorrect state boundaries.
Inspect the circuit and correct the fault.
Constraints
- Do not modify the clock network or flip-flop clock pins.
- Do not replace the flip-flops.
- Only modify the combinational logic feeding the flip-flop inputs.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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