4-Bit Synchronous Counter with Terminal Count
Cascading multiple counters to form larger timers or dividers requires a clean synchronization signal. The terminal count output provides this cascade interface by signaling exactly when the counter reaches its maximum value.
Implement a 4-bit synchronous up-counter with a synchronous reset. The counter increments its 4-bit output Q on every rising edge of the clock. When rst is 1, Q resets to 0 on the next clock edge. The terminal count output TC is a combinational signal that goes high only when all bits of Q are 1.
| Q[3] | Q[2] | Q[1] | Q[0] | TC | |--------|--------|--------|--------|------| | 0 | 1 | 1 | 1 | 0 | | 1 | 0 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 | 0 | | 1 | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 | 1 |
Constraints
TCmust be driven by combinational logic directly from theQoutputs.- Do not use asynchronous resets.
TCmust strictly be 0 for states 7, 11, and 13.
Topics
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