Cascaded 4-Bit Synchronous Counters
Two 4-bit synchronous counters are cascaded to form an 8-bit counter. The lower counter increments on every positive edge of CLK when EN is HIGH. The upper counter increments on the positive edge of CLK only when the lower counter's terminal count (TC0) is HIGH. TC0 evaluates to HIGH strictly when the lower counter is at 15 and EN is HIGH.
Four signals are shown: CLK (clock, period 2), EN (master enable input), TC0 (terminal count output of the lower stage), and Q1_0 (LSB output of the upper stage). The lower counter starts at a value of 14 (1110) and the upper counter starts at 0 (0000).
Trace TC0 and Q1_0 across all 12 time steps.
Constraints
- Both counters are strictly positive-edge-triggered.
TC0is a combinational output that depends on the lower counter's current state and the current value ofEN.- The upper counter evaluates
TC0exactly at the rising edge ofCLK.
Topics
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