Synchronous Counter with Synchronous Load
Programmable starting points for arbitrary waveform generation, pulse-width modulation, and frequency synthesis require counters that can jump to specific states. A synchronous load counter allows the system to overwrite the current count value directly from a data bus on the active clock edge.
The circuit maintains a 4-bit state Q. On the rising edge of clk, the load signal determines whether the counter captures the 4-bit input D or increments its current value. The load signal strictly overrides the increment operation. An asynchronous rst signal clears the counter to 0.
| rst | load | clk | Q_next | |-------|--------|-------|----------| | 1 | X | X | 0 | | 0 | 1 | ↑ | D | | 0 | 0 | ↑ | Q + 1 |
Constraints
- Use standard D flip-flops for state retention.
- Implement the load priority using a 2:1 multiplexer structure at the D input of each flip-flop.
- Do not use asynchronous preset or clear pins to implement the load functionality.
Topics
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