4-Digit BCD Counter: 0000 to 9999
Digital panel meters and frequency counters rely on multi-stage binary-coded decimal (BCD) counters to drive human-readable displays. A four-digit BCD counter cascades four individual decade stages to count from 0000 to 9999.
The module receives an active-high synchronous RESET and an active-high enable EN. The output consists of four 4-bit buses: Q0 for ones, Q1 for tens, Q2 for hundreds, and Q3 for thousands.
When EN is 1, the counter increments by one on each rising clock edge. When EN is 0, the counter holds its current value. When RESET is 1, all four digits synchronously clear to 0 regardless of the enable state.
Proper cascade logic is required to maintain synchronous operation. The tens digit Q1 increments only when the ones digit Q0 is 9 and EN is high. The hundreds digit Q2 increments only when both Q0 and Q1 are 9. The thousands digit Q3 increments only when Q0, Q1, and Q2 are all 9. The entire counter must roll over from 9999 to 0000.
Constraints
- Implement using synchronous design practices.
- Cascade four distinct BCD stages.
- Do not implement a 14-bit binary counter followed by binary-to-BCD conversion.
- Gate each cascade enable with all lower-stage terminal counts.
Topics
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