BCD Counter with Enable: Count Preservation
A positive-edge-triggered BCD counter increments its value from 0 to 9 on the rising edge of CLK when EN is HIGH, and holds its current value when EN is LOW.
Six signals are shown: CLK (clock), EN (enable input), and Q3, Q2, Q1, Q0 (outputs representing the 4-bit BCD value, initially 6 or 0110).
Trace the outputs Q3, Q2, Q1, and Q0 across all 16 time steps.
Constraints
- The counter rolls over directly from 9 (1001) to 0 (0000).
- State changes only occur exactly on the LOW-to-HIGH transitions of
CLK. - The
ENsignal must be evaluated exactly at the moment of the clock edge.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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