Asynchronous Reset Pulse Shortener
Interrupt controllers and high-speed communication interfaces often need to clear a status flag the exact moment it is acknowledged, without waiting for the next clock edge. The self-resetting register accomplishes this by routing its own output back into its asynchronous clear pin to generate a combinational-delay pulse.
Construct a self-resetting register circuit. The output q must capture the input d on the rising edge of clk. The moment q transitions to 1, it must immediately drive the flip-flop's asynchronous reset pin to clear itself back to 0. The circuit must also support an external reset: if the input rst is 1, the flip-flop must asynchronously clear regardless of its current state.
Port Definition
| Port | Direction | Width | Description | |------|-----------|-------|-------------| | clk | Input | 1-bit | Clock signal | | d | Input | 1-bit | Data input | | rst | Input | 1-bit | External asynchronous reset | | q | Output | 1-bit | Self-clearing output pulse |
Constraints
- Use exactly one D flip-flop with an active-high asynchronous reset.
- Drive the flip-flop's reset pin using only combinational logic.
- Do not use delay elements to artificially widen the pulse.
- Route the flip-flop's output directly to the primary output
q.
Topics
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