Shift Register Delayed Pulse
Pipelined datapaths require control signals to travel alongside the data through various stages of execution. To maintain synchronization across the system, a control pulse must often be delayed by a fixed number of clock cycles to match the pipeline depth.
The circuit receives a single-cycle high signal on pulse_in. It must output an identical single-cycle high signal on pulse_out exactly four clock cycles later. The system operates on the rising edge of clk and uses an active-high, synchronous rst.
| Cycle | rst | pulse_in | pulse_out | |-------|-------|------------|-------------| | 0 | 1 | 0 | 0 | | 1 | 0 | 1 | 0 | | 2 | 0 | 0 | 0 | | 3 | 0 | 0 | 0 | | 4 | 0 | 0 | 0 | | 5 | 0 | 0 | 1 | | 6 | 0 | 0 | 0 |
Constraints
- Use only D flip-flops to construct the delay path.
- Implement exactly a 4-cycle delay between input and output.
- Clear all internal state when the synchronous active-high
rstis asserted.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.