CodiodeCodiode
Home
Problem Solving
Skill Tracks
My Assignments
Contests
Leaderboard
Community
Settings
Codiode/Problems/Sequential Logic

Pulse Stretcher

MediumLogic CircuitBuild

Fast control signals and single-cycle events are easily missed by slower downstream clock domains or human-visible LED indicators. A pulse stretcher captures a brief event and holds it active long enough to guarantee detection.

Design a circuit that extends a 1-cycle input pulse into exactly a 4-cycle output pulse. When din is 1, dout must assert to 1 in the same clock cycle and remain 1 for a total of four consecutive cycles. Any additional assertions of din while the output is already stretching must be completely ignored.

| rst | din | State | dout | |-------|-------|-------|--------| | 1 | X | Reset | 0 | | 0 | 1 | Idle | 1 | | 0 | X | Busy | 1 | | 0 | 0 | Idle | 0 |

Constraints

  • Implement a synchronous active-high reset.
  • Assert dout in the exact same cycle that din first goes high.
  • Ignore all subsequent assertions of din during an active 4-cycle stretch operation.

Topics

timingstate-machineinterface

Solve this problem

Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.

This problem is part of Codiode Pro. The statement above is free to read.

Sign in to solveSee what Pro unlocks

The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.

Related problems

  • 3-bit Ripple Counter from Toggle Flip-FlopsEasy
  • D Latch from a 2:1 MUXEasy
  • 2-bit Ring CounterEasy
  • T Flip-Flop from a D Flip-FlopEasy
  • Handshake Deadlock Due to Early ResetHard
  • Reconvergence of Individually Synchronized BitsHard
  • Debug: Asynchronous Clear GlitchHard
  • Clock Gate Enable Crossing DomainsHard

Browse all problems · Learning tracks