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Codiode/Problems/Sequential Logic

Monostable Multivibrator Timing

HardLogic CircuitTiming Diagram

A non-retriggerable monostable multivibrator is built using a positive-edge-triggered D flip-flop with its D input tied HIGH and an RC delay network driving its asynchronous active-low clear pin. A LOW-to-HIGH transition on TRIG sets Q to 1. The RC network automatically clears Q back to 0 exactly 3 time steps after Q goes HIGH, regardless of the CLK state. Rising edges on TRIG that occur while Q is already HIGH are ignored because the flip-flop is already set and the RC timer is not reset.

Three signals are shown: CLK (reference clock, period 2), TRIG (trigger input), and Q (output, initially 0).

Trace Q across all 16 time steps.

Constraints

  • Q transitions to 1 only on the LOW-to-HIGH transition of TRIG.
  • Q transitions to 0 exactly 3 time steps after transitioning to 1.
  • The clear operation is completely asynchronous and does not wait for a CLK edge.

Topics

Sequential LogicAsynchronousMultivibratorRC Delay

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