Digital One Shot Timer
Hardware systems frequently require a fixed-duration pulse to drive mechanical components, debounce switches, or sequence power rails. The digital one-shot timer replaces legacy analog RC timers with deterministic, counter-based synchronous logic.
The circuit receives a trigger signal. Upon detecting a high trigger, the output pulse must assert high for exactly 100 clock cycles. The timer is non-retriggerable: any trigger assertions occurring while pulse is high must be ignored. After 100 cycles, pulse deasserts and the timer waits for the next trigger. An active-high rst signal resets the timer state and drives pulse low immediately.
Constraints
- Use synchronous logic only.
- Ignore all incoming triggers while the timer is active.
- Drive the
pulseoutput high for exactly 100 clock cycles following a valid trigger. - Implement using only standard flip-flops and combinational logic.
- Do not use asynchronous delays or RC elements.
Topics
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