Programmable Edge Detector Selection
Reusable intellectual property blocks often need configurable interrupt polarities to interface with various external peripherals. A programmable edge detector allows a host system to dynamically select which signal transitions trigger a synchronized, one-cycle interrupt pulse.
The circuit monitors the din input and generates a single-cycle high pulse output based on the control signals mode_1 and mode_0. An implicit synchronous clock drives the detection logic.
| mode_1 | mode_0 | Detected Edge | pulse Output Condition | |----------|----------|---------------|--------------------------| | 0 | 0 | None | Always 0 | | 0 | 1 | Rising | din transitions 0 to 1 | | 1 | 0 | Falling | din transitions 1 to 0 | | 1 | 1 | Both | Any din transition |
Constraints
- Synchronize all state elements to a single clock domain.
- Produce an output pulse exactly one clock cycle wide for each valid transition.
- Do not use asynchronous delay elements or RC timing techniques.
Topics
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