Bidirectional SR: Boundary Condition at Stage 0 and Stage 3
A 4-bit bidirectional shift register shifts its contents right or left on every LOW-to-HIGH transition of CLK.
Eight signals are shown: CLK (clock, positive-edge triggered), DIR (direction control), SER_R (right-shift serial input), SER_L (left-shift serial input), and four outputs Q0, Q1, Q2, Q3 (all initially 1). During a right-shift (DIR=1), Q0 receives SER_R, Q1 receives Q0, Q2 receives Q1, and Q3 receives Q2. During a left-shift (DIR=0), Q3 receives SER_L, Q2 receives Q3, Q1 receives Q2, and Q0 receives Q1.
Trace outputs Q0, Q1, Q2, and Q3 across all 16 time steps.
Constraints
- The outputs only change state on the rising edge of
CLK. - Boundary stages must receive the correct serial input (
SER_RorSER_L) during a shift, rather than recirculating their own previous value.
Topics
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