Cascaded Clock Gating Logic
Complex subsystems often have multiple reasons to sleep, such as software overrides, idle timers, and thermal throttling. Combining these conditions safely requires integrating multiple enable signals before driving the final clock gate to prevent downstream glitches.
The circuit must generate a glitch-free gated clock gclk. The subsystem runs only when en_sw, en_idle, and en_therm are all asserted high. Combine these three signals into an intermediate signal en_comb according to the following logic:
| en_sw | en_idle | en_therm | en_comb | |---------|-----------|------------|-----------| | 0 | 0 | 0 | 0 | | 0 | 0 | 1 | 0 | | 0 | 1 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | 0 | 0 | 0 | | 1 | 0 | 1 | 0 | | 1 | 1 | 0 | 0 | | 1 | 1 | 1 | 1 |
Feed en_comb into a standard Integrated Clock Gating (ICG) structure. When clk is low, the ICG must capture and latch en_comb. When clk is high, the latched value must hold steady, ignoring any changes to the input enables. Finally, gclk must follow clk if the latched enable is high, and remain low if the latched enable is low.
Constraints
- Combine all enable signals combinationally before feeding them to the clock gating cell.
- Use exactly one active-low D-latch to hold the combined enable condition.
- Gate the clock using a single AND gate driven by the latch output and
clk. - Do not gate
clkdirectly with unlatched combinational signals.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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