Clock Gating Setup Time Violation
A standard integrated clock gating (ICG) cell uses a negative-level-sensitive latch to prevent glitches, but a late enable signal will cause a setup time violation. The latch output (LATCH_OUT) follows EN when CLK is LOW and holds its value when CLK is HIGH. If EN transitions at the exact step CLK transitions from LOW to HIGH, LATCH_OUT becomes metastable (X) for that holding phase. The final output GATED_CLK is the logical AND of CLK and LATCH_OUT.
Four signals are shown: CLK (clock, period 2), EN (input), LATCH_OUT (intermediate output, initially 0), and GATED_CLK (final output, initially 0). Trace LATCH_OUT and GATED_CLK across all 12 time steps, using X to represent unknown or metastable states.
Constraints
- You must use the character
Xto represent any time step where a signal is metastable or indeterminate. - Evaluate the AND gate logic strictly at each time step. Remember that
0 AND X = 0, but1 AND X = X.
Topics
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