Negative Edge Integrated Clock Gating Cell
Mixed-edge domains require clock gating cells tailored to the active edge of the sequential logic. For negative-edge triggered flip-flops, gating the clock incorrectly can prematurely trigger or swallow the active falling edge.
The clock gating cell must pass clk to gclk when en is 1. When en is 0, the output gclk must be held HIGH (1) to safely suppress any falling edges. The enable signal must be synchronized to clk to prevent glitches from propagating to the output.
| en (stable) | clk | gclk | |---------------|-------|--------| | 0 | 0 | 1 | | 0 | 1 | 1 | | 1 | 0 | 0 | | 1 | 1 | 1 |
Constraints
- Use exactly one positive level-sensitive D-latch.
- Use exactly one OR gate.
- Use exactly one NOT gate.
- Do not use edge-triggered flip-flops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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