Positive Edge Integrated Clock Gating Cell
Modern low-power ASIC designs aggressively shut down clock trees to idle logic blocks. A glitch-free integrated clock gating cell safely passes or blocks the clock signal without introducing spurious edges that corrupt downstream flip-flops.
Construct a positive-edge integrated clock gating cell. The circuit must gate the input clock clk based on the enable signal en. To prevent glitches, the enable signal must be synchronized such that it only propagates to the gating logic when clk is low. The output clock gclk follows clk when the synchronized enable is high, and remains low when the synchronized enable is low.
| clk | en | Internal Latched en | gclk | |-------|------|-----------------------|--------| | 0 | 0 | 0 | 0 | | 0 | 1 | 1 | 0 | | 1 | X | Hold previous state | Internal Latched en |
Constraints
- Use exactly one negative level-sensitive latch to synchronize the enable signal.
- Use exactly one 2-input AND gate for the final clock gating.
- Do not use edge-triggered flip-flops.
- Do not use combinational feedback loops.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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