Naive OR Gate Clock Gating Glitch
A naive clock gating circuit uses a purely combinational OR gate to force the clock high when idle. The output GATED_CLK is the immediate logical OR of CLK and EN.
Three signals are shown: CLK (clock, period 2), EN (gating control input) and GATED_CLK (output).
Trace GATED_CLK across all 10 time steps to reveal the false edges created by changing EN while CLK is LOW.
Constraints
- The combinational delay of the OR gate is assumed to be zero.
- The output responds immediately to any change in the inputs.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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