Chip Select Lead and Lag Timing
SPI peripherals require precise framing to sample data correctly. The Chip Select line must be stable before the clock begins toggling and remain held after the final clock edge to ensure the transaction completes cleanly.
Design a synchronous state machine that controls an active-low chip select (cs_n) and a clock enable (sck_en) based on a transaction request (req). The system is clocked by an implicit global clock.
| Cycle | req | State Phase | cs_n | sck_en | |-------|-------|-------------|--------|----------| | 0 | 0 | Idle | 1 | 0 | | 1 | 1 | Lead | 0 | 0 | | 2 | 1 | Active | 0 | 1 | | 3 | 1 | Active | 0 | 1 | | 4 | 0 | Lag | 0 | 0 | | 5 | 0 | Idle | 1 | 0 |
Assume req will always remain asserted for at least two consecutive cycles during a transaction. Assume req will remain deasserted for at least one cycle between transactions.
Constraints
- Implement a synchronous Moore state machine.
- Use the active-high synchronous reset
rstto return the system to the Idle state. - Derive
cs_nandsck_enstrictly from the current state register.
Topics
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