SPI Master 8-Bit Transfer
Serial Peripheral Interface (SPI) masters control transaction lengths by driving the clock line for a precise duration. To prevent data corruption, the controller must halt the clock and return to idle exactly after the 8-bit payload is exchanged.
The circuit waits in an idle state until the start signal is asserted. Once triggered, it drives the active signal high for exactly 8 clock cycles to frame the transaction. During the 8th and final cycle of the transaction, the done signal must assert high. On the following clock edge, the circuit must return to the idle state.
| State | start | active | done | Next State | |-------|---------|----------|--------|------------| | IDLE | 0 | 0 | 0 | IDLE | | IDLE | 1 | 0 | 0 | ACTIVE (Cycle 1) | | ACTIVE (Cycles 1-7) | X | 1 | 0 | ACTIVE (Cycle N+1) | | ACTIVE (Cycle 8) | X | 1 | 1 | IDLE |
Constraints
- Implement a synchronous state machine driven by a single clock.
- Use an active-high synchronous reset
rst. - The
donesignal must assert high exclusively during the 8th cycle of the active transaction. - The
activesignal must transition to low immediately after the 8th cycle.
Topics
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