SPI Full Duplex Shift Register
Serial Peripheral Interface (SPI) controllers inherently swap data between master and slave devices in a circular buffer fashion. A single core register handles simultaneous transmission and reception to complete a full-duplex data exchange.
Implement an 8-bit shift register that processes data on the rising edge of clk. When rst is high, the register asynchronously clears to zero. When load is high, the register synchronously loads the 8-bit parallel value data_in. When load is low, the register shifts its contents left by one bit position. During a shift, the incoming bit from MISO is shifted into the least significant bit (LSB). The MOSI output must continuously reflect the current most significant bit (MSB) of the register, and data_out must reflect the full 8-bit parallel state.
Constraints
- Implement synchronous parallel load and left-shift operations.
- Implement an asynchronous active-high reset.
MOSImust continuously output bit 7 of the current register state.
Topics
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