SPI Slave MOSI Sampler
Embedded systems rely on SPI for high-speed sensor and peripheral communication. A robust SPI slave cannot use the incoming serial clock directly as a register clock due to domain crossing hazards.
The circuit must oversample the incoming asynchronous SCK and MOSI signals using the system clock. It must synchronize SCK through a 2-stage flip-flop synchronizer. A third flip-flop must keep the previous state of the synchronized clock to detect a rising edge. Upon detecting a rising edge, the circuit must capture the current MOSI value into the data_out register and assert a registered valid signal high for exactly one clock cycle.
Constraints
- Use only synchronous elements clocked by the implicit system clock.
- Do not use
SCKas a clock input to any flip-flop. - Implement exactly a 2-stage synchronizer for the
SCKinput before edge detection.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.