SPI Slave MISO Driver
SPI slave devices must present data to the master with sufficient setup time before the sampling edge. By driving the miso line on the falling edge of the oversampled serial clock, the slave ensures the master reads stable data on the subsequent rising edge.
The circuit operates on an implicit fast internal system clock. The external SPI clock sck is oversampled to detect transitions.
- When
rstis 1, the internal 8-bit shift register clears to 0. - When
loadis 1, the shift register loads the 8-bitdata_in. - When
loadis 0 and a falling edge is detected onsck, the register shifts left by one bit. A 0 is shifted into the LSB. - The output
misocontinuously reflects the most significant bit (bit 7) of the shift register.
Constraints
- Use a synchronous active-high reset.
- Implement an edge detector to find the 1-to-0 transition of
sck. - Shift data out MSB first.
- Drive
misocombinationally from the MSB of the shift register.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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