SPI Slave CS Reset Logic
Serial Peripheral Interface (SPI) slaves must gracefully handle aborted transactions. When a master deasserts the chip select line before a full byte is transferred, the slave must immediately discard the partial data and reset its internal state.
Construct the bit counter for an SPI slave. The circuit must maintain a 3-bit output bit_cnt that increments on every clock cycle while the active-low chip select CS is 0. If CS is 1, bit_cnt must synchronously reset to 0 on the next clock edge. The counter wraps back to 0 after reaching 7.
| CS | Next bit_cnt | |------|----------------| | 1 | 0 | | 0 | bit_cnt + 1 |
Constraints
- Implement the reset behavior synchronously.
- Do not use asynchronous reset pins on the flip-flops.
- Build the counter using standard D flip-flops and combinational logic.
Topics
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Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
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