Multi Byte SPI Master
Reading from flash memory or streaming sensor data requires burst mode transactions. The SPI master must assert chip select and maintain the clock across multiple byte boundaries without interruption.
The circuit receives a 1-bit start signal and a 2-bit length input indicating the number of bytes to transfer. Upon detecting start high, it drives the 1-bit cs_n output low and sets the 1-bit busy output high. It then generates continuous pulses on the 1-bit sck output until exactly length multiplied by 8 bits are transferred. The cs_n signal must remain strictly low between bytes to maintain the burst transaction. Once all bits are transferred, cs_n returns high and busy returns low. Assume sck goes high on the first active clock cycle and toggles on every subsequent clock cycle.
Constraints
- Implement synchronous logic driven by the
clksignal. - Reset all internal state and counters when the active-high
rstsignal is asserted. - Do not deassert
cs_nbetween bytes during a continuous multi-byte transfer.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.