SPI Command Decoder
Serial peripheral interface (SPI) slaves must determine the master's intent before transferring payload data. The first byte of an SPI transaction often serves as a command header where the most significant bit (MSB) indicates a read or write operation.
Construct a sequential circuit that decodes the first byte of an SPI transaction. The circuit resets and remains idle while the active-low chip select cs_n is 1. When cs_n is 0, the circuit samples the mosi input on each rising edge of clk. The first sampled bit is the transaction MSB. Exactly on the 8th rising edge of clk, the circuit must assert valid to 1. Simultaneously, it must assert read to 1 if the MSB was 1, or assert write to 1 if the MSB was 0.
Constraints
- Clear all outputs to 0 immediately when
cs_nis 1. - Sample
mosistrictly on the rising edge ofclk. - Assert
valid,read, andwriteonly on the 8th rising edge ofclkaftercs_ngoes low. - Hold the asserted output states as long as
cs_nremains 0.
Topics
Solve this problem
Place the gates, wire them up and watch the signals settle. Every submission runs on the same simulation engine that grades it.
This problem is part of Codiode Pro. The statement above is free to read.
The circuit builder and code editor need a desktop screen. On a phone, read the problem here and open it on a laptop to solve.