SPI Dummy Byte Generator
SPI masters must actively toggle the serial clock to receive data from a slave device. This is achieved by transmitting a dummy byte, typically hex FF, to force clock generation while simultaneously sampling the incoming data line.
When the read_en signal is asserted high for one clock cycle, the circuit must initiate an 8-cycle read operation. During these 8 cycles, the mosi output must be driven high continuously to transmit the FF dummy byte. Concurrently, the circuit must shift the miso input into an internal 8-bit register, MSB first. The data_out port must continuously output the state of this shift register.
On the clock cycle immediately following the 8th shifted bit, the valid output must be asserted high for exactly one cycle, indicating that data_out holds the complete captured byte. When no read operation is in progress, mosi and valid must remain low.
Constraints
- Implement a synchronous active-high reset using the
rstsignal. - Drive
mosilow when the circuit is not actively executing an 8-cycle read operation. - Shift the incoming
misodata MSB first. - Do not initiate a new read operation if
read_enis asserted while a read is already in progress.
Topics
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