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Codiode/Problems/Sequential Logic

I2C Start Condition Detector

MediumLogic CircuitBuild

I2C peripherals lack a dedicated chip select line to indicate the start of a transaction. Instead, every device on the bus continuously monitors the data and clock lines for a specific protocol signature.

The circuit must assert start_flag for exactly one clock cycle when a valid I2C Start condition occurs. A Start condition is defined as a high-to-low transition on the serial data line SDA while the serial clock line SCL remains strictly high.

| SCL | SDA_prev | SDA | start_flag | |-------|------------|-------|--------------| | 0 | X | X | 0 | | 1 | 0 | X | 0 | | 1 | 1 | 1 | 0 | | 1 | 1 | 0 | 1 |

*Note: SDA_prev represents the sampled value of SDA from the previous clock cycle.*

Constraints

  • Use synchronous logic triggered on the rising edge of clk.
  • Implement an active-low asynchronous reset using rst_n.
  • The start_flag output must remain asserted for exactly one clock cycle per valid sequence.

Topics

Edge DetectionProtocolI2C

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