I2C Stop Condition Detector
Every I2C slave device monitors the bus to determine when a transaction concludes and the bus is free. The stop condition is the universal signal that a master has released the bus.
The detector must monitor the serial clock SCL and serial data SDA lines. It asserts the Stop output for exactly one clock cycle when SDA transitions from 0 to 1 while SCL is strictly 1. All signals are synchronous to the implicit system clock.
| rst | SCL | SDA_prev | SDA_curr | Stop | |-------|-------|------------|------------|--------| | 1 | X | X | X | 0 | | 0 | 0 | X | X | 0 | | 0 | 1 | 0 | 0 | 0 | | 0 | 1 | 0 | 1 | 1 | | 0 | 1 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 0 |
Constraints
- Use standard D flip-flops for state storage.
- The reset signal
rstis synchronous and active-high. - The
Stopoutput must assert for exactly one clock cycle per valid transition.
Topics
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