I2C Clock Stretching Detector
I2C masters must accommodate slow slave devices that pause communication by holding the clock line low. This flow control mechanism requires the master to monitor the physical bus state against its own intended output.
When the master attempts to drive the clock high (scl_out is 1) but the physical bus remains low (scl_in is 0), clock stretching is active. The circuit must output a registered signal stretch_det that asserts high under this condition.
| scl_out | scl_in | Next stretch_det | |-----------|----------|--------------------| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 1 | | 1 | 1 | 0 |
Constraints
- Use a D flip-flop to register the
stretch_detoutput. - Implement an active-low synchronous reset using the
rst_nsignal. - Evaluate the stretch condition using strictly combinational logic before the register.
Topics
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